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| SRAMs-3.3-6/96 Memory ATL60 SRAMs Compiled Gate Level Compiled Gate Level SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Single Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Common Dual Port SRAM Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Single Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Best Case Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Typical Case Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Worst Case Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Dual Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Best Case Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Typical Case Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Worst Case Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9-1 SRAMs-3.3-6/96 Compiled Gate Level SRAMs Atmel offers a variety of compiled gate level SRAMs for the ATL60 series of gate arrays. These static asynchronous SRAMs utilize the personalization layers and occupy standard gate array sites. The SRAMs come in either dual port or single port architectures. The dual port SRAMs have two sets of address inputs, a read address (RD_ADDR) and a write address (WR_ADDR). The output of the SRAM is the word which is pointed to by the read address. When the WE (Write Enable) input goes low, the word on the DIN bus is written to the address specified by the write address. The single port SRAMs have one set of address inputs (ADDR) which control both write and read operations. The output of the SRAM is always the word which is pointed to by the address inputs. When the WRITE input goes low, the word on the DIN bus is written to the address specified by the address input. Both single port and dual port SRAMs have enables (OE) on their outputs. The outputs stay high while the output enable signal is high. The SRAMs can be compiled in depths ranging from 2 words to 32 words. The following tables give size information for some common SRAM sizes. Contact Atmel for the exact size of any SRAM not listed. Common Single Port SRAM Sizes SRAM Width (bits) 8 4 12 16 24 32 294 sites PRAM4X8SUB32 378 sites PRAM4X12SUB32 630 sites PRAM8X12SUB32 882 sites 462 sites PRAM4X16SUB32 770 sites PRAM8X16SUB32 1078 sites 630 sites PRAM4X24SUB32 1050 sites PRAM8X24SUB32 1470 sites 798 sites PRAM4X32SUB32 1330 sites PRAM8X32SUB32 1862 sites Depth (words) 8 490 sites PRAM8X8SUB32 12 686 sites PRAM12X8SUB32 PRAM12X12SUB32 PRAM12X16SUB32 PRAM12X24SUB32 PRAM12X32SUB32 16 882 sites 1134 sites 1386 sites 1890 sites 2394 sites PRAM16X8SUB32 PRAM16X12SUB32 PRAM16X16SUB32 PRAM16X24SUB32 PRAM16X32SUB32 24 1274 sites PRAM24X8 1638 sites PRAM24X12 2142 sites PRAM32X12 2002 sites PRAM24X16 2618 sites PRAM32X16 2730 sites PRAM24X24 3570 sites PRAM32X24 3458 sites PRAM24X32 4522 sites PRAM32X32 32 1666 sites PRAM32X8 9-2 Cell Library SRAMs-3.3-6/96 Common Dual Port SRAM Sizes SRAM Width (bits) 8 4 360 sites PRAM4X8DSUB32 8 DEPTH (words) 570 sites PRAM8X8DSUB32 12 780 sites PRAM12X8DSUB32 16 990 sites PRAM16X8DSUB32 24 1410 sites PRAM24X8D 1830 sites 32 PRAM32X8D PRAM32X12D PRAM32X16D PRAM32X24D PRAM32X32D 12 456 sites PRAM4X12DSUB32 722 sites PRAM8X12DSUB32 988 sites 16 552 sites PRAM4X16DSUB32 874 sites PRAM8X16DSUB32 1196 sites 24 744 sites PRAM4X24DSUB32 1178 sites PRAM8X24DSUB32 1612 sites 32 936 sites PRAM4X32DSUB32 1482 sites PRAM8X32DSUB32 2028 sites PRAM12X12DSUB32 PRAM12X16DSUB32 PRAM12X24DSUB32 PRAM12X32DSUB32 1254 sites 1518 sites 2046 sites 2574 sites PRAM16X12DSUB32 PRAM16X16DSUB32 PRAM16X24DSUB32 PRAM16X32DSUB32 1786 sites PRAM24X12D 2318 sites 2162 sites PRAM24X16D 2806 sites 2914 sites PRAM24X24D 3782 sites 3666 sites PRAM24X32D 4758 sites Below are symbols for 4 x 4 single and dual port SRAMs (PRAM4X4SUB32 and PRAM4X4SUB32). Note that the unused address inputs must be tied to VSS or the SRAM will not function properly (i.e. ADDR4 is tied low for SRAMs smaller than 18 words, ADDR3 for SRAMs smaller than 10 words, ADDR2 for SRAMs smaller than 6 words, and ADDR1 for a 2 word SRAM). Unused RD_ADDR and WR_ADDR inputs need to be tied to VSS for dual port SRAMs. The SRAMs can be multiplexed to create a deeper SRAM. PRAM4X4SUB32 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 DIN0 DIN1 DIN2 DIN3 OE WE DOUT0 DOUT1 DOUT2 DOUT3 PRAM4X4DSUB32 DIN0 DIN1 DIN2 DIN3 OE RD_ADDR0 RD_ADDR1 RD_ADDR2 RD_ADDR3 RD_ADDR4 WE WR_ADDR0 WR_ADDR1 WR_ADDR2 WR_ADDR3 WR_ADDR4 DOUT0 DOUT1 DOUT2 DOUT3 9-3 SRAMs-3.3-6/96 PRAM48X4 BUF2 ADDR0 BUF2 ADDR1 BUF2 ADDR2 BUF2 ADDR3 BUF2 ADDR4 ADDR5 A0 A1 A2 A3 A4 INV2 A5 INV2 A5BAR A0 A1 A2 A3 A4 D0 D1 D2 D3 A5 WE0 ADDR0 DOUT0 ADDR1 DOUT1 ADDR2 DOUT2 ADDR3 DOUT3 ADDR4 DIN0 PRAM32X4 DIN1 DIN2 DIN3 OE WE NAN2H DOUT0 NAN2H DOUT1 NAN2H DOUT2 NAN2H DOUT3 INV2 DIN0 INV2 DIN1 INV2 DIN2 INV2 DIN3 D0 D1 D2 D3 A0 A1 A2 A3 D0 D1 vss! D2 D3 A5BAR WE1 WE A5 A5BAR ORR2 WE0 WE1 ORR2 ADDR0 DOUT0 ADDR1 DOUT1 ADDR2 DOUT2 ADDR3 DOUT3 ADDR4 DIN0 PRAM16X4 DIN1 DIN2 DIN3 OE WE The following pages contain the SRAM write and read timing which was gathered from running Spice simulations. The write timing was determined by measuring the propagation delay from the WRITE, ADDR, and DIN pins to the memory latch bit on a large (32x36) and small (2x2) SRAM. The times given were measured from the input pins to when the actual data in memory changed. This was done by initializing the SRAM to a specific state such that if only the input pin under analysis changed, the memory bit would be changed. The delays were measured for the memory bit rising and falling. The longest path to a memory latch bit on the large SRAM represents the maximum delay and the shortest path to a memory latch bit on the small SRAM represents the minimum delay. The setup and hold timing were derived from these delays. The equations used are given with the specifications. The read t i m i n g w a s d e t e r m i n ed b y m ea s u r i n g t h e propagation delay through the SRAMs. These Spice simulations were run with best, typical, and worst temperature and process conditions. Four unit loads were applied to the SRAM outputs for the Spice simulations. 9-4 Cell Library SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Single Port Operation 0.6 Conditions Best Case Process, Temperature (T = -55) Voltage (VDD = 5.5 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 x .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (SP2x2) MAXIMUM (SP32x36) 0.96 ns 1.54 ns 1.96 ns 0.68 ns WRITE ADDR DIN WRITE ADDR DIN MEMLATCH WRITE (r) WRITE (f) ADDR DIN = = = = = = 1.13 ns 0.14 ns 0.56 ns 0.93 ns 1.54 ns 2.06 ns 0.12 ns 0.83 ns 0.82 ns 0.03 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 1.96 ns - 0.83 ns 0.96 ns - 0.82 ns 0.68 ns - 0.12 ns 0.96 ns - 0.03 ns 1.13 ns + 0.93 ns Read Timing MINIMUM (DP2x2) PDA-D ADDR PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 2.29 ns 1.18 ns 0.68 ns 0.07 ns OE DOUT 9-5 SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Single Port Operation 0.6 Conditions Typical Case Process, Temperature (T = 25) Voltage (VDD = 5.0 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 x .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (SP2x2) MAXIMUM (SP32x36) 1.51 ns 2.29 ns 3.02 ns 0.92 ns WRITE ADDR DIN WRITE ADDR DIN MEMLATCH WRITE (r) WRITE (f) ADDR DIN 0.36 ns 1.13 ns 1.42 ns 0.20 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 3.02 ns - 1.13 ns 1.51 ns - 1.42 ns 0.92 ns - 0.36 ns 1.51 ns - 0.20 ns 1.89 ns + 1.31 ns = = = = = = 1.89 ns 0.09 ns 0.56 ns 1.31 ns 2.29 ns 3.20 ns Read Timing ADDR PDA-D MINIMUM (DP2x2) PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 3.52 ns 1.64 ns 1.17 ns 0.20 ns OE DOUT 9-6 Cell Library SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Single Port Operation 0.6 Conditions Worst Case Process, Temperature (T = 125) Voltage (VDD = 4.5 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 x .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (SP2x2) MAXIMUM (SP32x36) 2.53 ns 3.70 ns 5.05 ns 1.18 ns WRITE ADDR DIN WRITE ADDR DIN MEMLATCH WRITE (r) WRITE (f) ADDR DIN = = = = = = 3.43 ns 0.03 ns 0.45 ns 2.02 ns 3.70 ns 5.45 ns 0.73 ns 1.62 ns 2.50 ns 0.51 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 5.05 ns - 1.62 ns 2.53 ns - 2.50 ns 1.18 ns- 0.73 ns 2.53 ns - 0.51 ns 3.43 ns + 2.02 ns Read Timing ADDR PDA-D MINIMUM (DP2x2) PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 5.93 ns 2.53 ns 2.13 ns 0.44 ns OE DOUT 9-7 SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Dual Port Operation 0.6 Conditions Best Case Process, Temperature (T=-55) Voltage (VDD = 5.5 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 X .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (DP2x2) MAXIMUM (DP32x36) 0.94 ns 1.57 ns 1.79 ns 0.68 ns WRITE ADDR DIN WRITE ADDR MEMLATCH DIN WRITE (r) WRITE (f) ADDR DIN = = = = = = 0.97 ns 0.39 ns 0.56 ns 0.86 ns 1.57 ns 1.83 ns 0.12 ns 0.82 ns 0.55 ns 0.08 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 1.79 ns - 0.82 ns 0.94 ns - 0.55 ns 0.68 ns - 0.12 ns 0.94 ns - 0.08 ns 0.97 ns + 0.86 ns Read Timing MINIMUM (DP2x2) PDA-D ADDR PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 2.27 ns 1.18 ns 0.65 ns 0.07 ns OE DOUT 9-8 Cell Library SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Dual Port Operation 0.6 Conditions Typical Case Process, Temperature (T=25) Voltage (VDD = 5.0 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 x .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (DP2x2) MAXIMUM (DP32x36) 1.48 ns 2.24 ns 2.59 ns 0.91 ns WRITE ADDR DIN WRITE ADDR DIN MEMLATCH WRITE (r) WRITE (f) ADDR DIN = = = = = = 1.48 ns 0.49 ns 0.55 ns 1.28 ns 2.24 ns 2.76 ns 0.36 ns 1.11 ns 0.99 ns 0.20 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 2.59 ns - 1.11 ns 1.48 ns - 0.99 ns 0.91 ns - 0.36 ns 1.48 ns- 0.20 ns 1.48 ns + 1.28 ns Read Timing ADDR PDA-D MINIMUM (DP2x2) PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 3.37 ns 1.64 ns 1.13 ns 0.20 ns OE DOUT 9-9 SRAMs-3.3-6/96 Compiled Gate Level SRAMs -- Dual Port Operation 0.6 Conditions Worst Case Process, Temperature (T = 125) Voltage (VDD = 4.5 Volts) Write Cycle Timing WRMINPWL WRMINPWH ADDRHOLD DATASU DATAHOLD Output Loading = 4 Unit Loads (4 x .033pf) Input Rise/Fall Time = 2 ns WRITE ADDR DIN ADDRSU Write Cycle Propagation Delay MINIMUM (DP2x2) MAXIMUM (DP32x36) 2.48 ns 3.63 ns 4.34 ns 1.18 ns WRITE ADDR DIN WRITE ADDR DIN MEMLATCH WRITE (r) WRITE (f) ADDR DIN = = = = = = 2.71ns 0.69 ns 0.46 ns 1.97 ns 3.63 ns 4.68 ns 0.72 ns 1.63 ns 1.79 ns 0.51 ns ADDRSU ADDRHOLD DATASU DATAHOLD WRMINPWL WRMINPWH = = = = = = ADDR (MAX) - WRITE (f) (MIN) WRITE (r) (MAX) - ADDR (MIN) DIN (MAX) - WRITE (r) (MIN) WRITE (r) (MAX) - DIN (MIN) WRITE (f) (MAX) ADDRSU + DATAHOLD = = = = = = 4.34 ns - 1.63 ns 2.48 ns - 1.79 ns 1.18 ns - 0.72 ns 2.48 ns - 0.51 ns 2.71 ns + 1.97 ns Read Timing ADDR PDA-D MINIMUM (DP2x2) PDA-D PDO-D PDO-D MAXIMUM (DP32x36) 5.66 ns 2.53 ns 2.01 ns 0.44 ns OE DOUT 9-10 Cell Library |
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